Summary: Researchers have created the first integrated “microwave brain” microchip that processes ultrafast data and wireless communication signals simultaneously. Using analog, nonlinear microwave physics instead of conventional digital logic, the chip performs real-time frequency-domain computations to decode radio signals, follow radar targets, and classify high-speed data streams. This approach delivers digital-like accuracy while consuming a fraction of the power, opening possibilities for secure wireless sensing and low-power edge computing.
Built and tested on a silicon microchip, the processor is a true microwave neural network that operates directly in the microwave frequency bands rather than relying on digital sampling and clocked processing. By leveraging intrinsic microwave behaviors, it sidesteps many conventional signal-processing steps, enabling extremely fast, energy-efficient computation for radio-frequency machine learning and communication tasks.
Key Facts:
- Analog microwave neural network: Computes across tens of gigahertz without discrete digital clock steps.
- High efficiency: Runs with under 200 milliwatts of power while achieving up to 88% accuracy on classification tasks.
- Broad applications: Suitable for radar tracking, wireless signal decoding, hardware security, and edge AI on portable devices.
Source: Cornell University
Overview
Cornell University researchers have developed a compact, low-power microchip they call a “microwave brain” — the first processor designed to compute using microwave physics. Described in Nature Electronics on August 11, the chip integrates an analog microwave neural network on silicon and performs broadband computation and communication tasks directly in the frequency domain.
Because the device exploits tunable microwave waveguides and strong nonlinear interactions, it can be programmed to transform microwave inputs across a wide frequency band instantaneously. Lead author Bal Govind, a doctoral student, explains that this programmable distortion across frequencies allows the same hardware to be repurposed for multiple computing and communications tasks without the stepwise processing typical of digital systems.
The network architecture uses coupled modes in tunable waveguides to form an analog neural network—an arrangement that recognizes patterns and adapts through training like other neural systems, but does so using continuous microwave physics rather than discrete digital operations. That analog, nonlinear behavior enables processing of data streams at tens of gigahertz, far above conventional digital chip clock rates.
Alyssa Apsel, co-senior author and professor of engineering, noted that the design departs from traditional circuit thinking. Instead of replicating the exact structure of digital neural networks, the team created a controlled mix of frequency interactions that collectively perform high-performance computation in hardware. Peter McMahon, co-senior author and associate professor of applied and engineering physics, also contributed to guiding the interdisciplinary effort.
Performance results show the processor handling both elementary logic operations and complex tasks, such as identifying bit sequences and counting binary values within multi-gigabit-per-second data. On multiple wireless-signal classification tasks, the chip reached accuracy levels at or above 88%, comparable to digital neural networks while requiring much less power and area.
Govind highlights the benefits of a probabilistic, analog approach: as computational tasks grow more complex, traditional digital systems need more circuitry, higher power budgets, and additional error correction to maintain accuracy. The microwave neural network, by contrast, sustains high accuracy without the same overhead, because computation emerges naturally from the device’s physical dynamics.
The chip’s sensitivity to small input changes makes it promising for hardware-based security and anomaly detection across multiple microwave bands. Researchers also see potential for true edge deployment: with further reductions in power consumption and continued integration with existing microwave and digital platforms, the technology could run native models on wearables, smartphones, or other edge devices without relying on cloud servers.
Although the chip remains experimental, the team is exploring ways to scale the architecture, improve accuracy, and combine it with standard microwave and digital processing. The device was fabricated using standard complementary metal–oxide–semiconductor (CMOS) technology and occupies a sub-wavelength footprint, supporting future integration into general-purpose analog processors.
Funding: The work originated within an exploratory effort of a larger project supported by the Defense Advanced Research Projects Agency and leveraged facilities at the Cornell NanoScale Science and Technology Facility, which receives partial support from the National Science Foundation.
About this neurotech research news
Author: Becka Bowyer
Source: Cornell University
Contact: Becka Bowyer – Cornell University
Image: The image is credited to Neuroscience News
Original Research: Closed access. “An integrated microwave neural network for broadband computation and communication” by Alyssa Apsel et al., Nature Electronics. DOI reference: 10.1038/s41928-025-01422-1
Abstract
An integrated microwave neural network for broadband computation and communication
Demand for high-bandwidth applications such as multi-gigabit communications and radar imaging requires ever-faster processing methods. In the microwave regime, where frequencies can exceed conventional clock rates, sampling and digital computation become challenging. This work reports an integrated microwave neural network that performs broadband computation and supports communication tasks directly in the microwave domain.
The microwave neural network operates across tens of gigahertz while being reprogrammed by comparatively slow control bitstreams in the megabit-per-second range. By exploiting strong nonlinearity in coupled microwave oscillations, the device expresses computation in a narrower readout spectrum, simplifying output measurement. The system searches for bit sequences within multi-gigabit-per-second data streams and emulates digital logic functions without bespoke circuits. It accelerates radio-frequency machine learning by classifying encoding schemes and detecting frequency shifts, enabling radar-based trajectory tracking and other sensing applications.
Fabricated with standard CMOS techniques, the network occupies an on-chip footprint of approximately 0.088 mm2 and consumes under 200 mW, making it amenable to integration into compact, energy-efficient analog processors and future edge-computing hardware.